STM32 Blue Pill Drivers
Drivers that could be used to interface and interact with STM32F103C8T6 Microcontroller
Loading...
Searching...
No Matches
t_RCC_CR Struct Reference

RCC clock control register. More...

#include "MCAL/RCC/RCC_private.h"

+ Collaboration diagram for t_RCC_CR:

Data Fields

t_u32 HSION: 1
 Internal high-speed clock enable. More...
 
t_u32 HSIRDY: 1
 Internal high-speed clock ready flag. More...
 
t_u32 __pad0__: 1
 Reserved bit(s) More...
 
t_u32 HSITRIM: 5
 Internal high-speed clock trimming. More...
 
t_u32 HSICAL: 8
 Internal high-speed clock calibration. More...
 
t_u32 HSEON: 1
 HSE clock enable. More...
 
t_u32 HSERDY: 1
 External high-speed clock ready flag. More...
 
t_u32 HSEBYP: 1
 External high-speed clock bypass. More...
 
t_u32 CSSON: 1
 Clock security system enable. More...
 
t_u32 __pad1__: 4
 Reserved bit(s) More...
 
t_u32 PLLON: 1
 PLL enable. More...
 
t_u32 PLLRDY: 1
 PLL clock ready flag. More...
 
t_u32 __pad2__: 6
 Reserved bit(s) More...
 

Detailed Description

RCC clock control register.

Field Documentation

◆ HSION

t_u32 HSION

Internal high-speed clock enable.

Enable or disable the internal high-speed clock (HSI)

◆ HSIRDY

t_u32 HSIRDY

Internal high-speed clock ready flag.

Whether the internal high-speed clock is ready or not

Warning
This field is read-only

◆ __pad0__

t_u32 __pad0__

Reserved bit(s)

Attention
This field is reserved and must be kept at reset value.

◆ HSITRIM

t_u32 HSITRIM

Internal high-speed clock trimming.

Adjusts the internal high-speed clock (HSI) frequency in conjunction with the HSICAL field

Note
Default value: 16

◆ HSICAL

t_u32 HSICAL

Internal high-speed clock calibration.

This field holds the factory calibration value

Warning
This field is read-only

◆ HSEON

t_u32 HSEON

HSE clock enable.

Enable or disable the external high-speed clock (HSE)

◆ HSERDY

t_u32 HSERDY

External high-speed clock ready flag.

Whether the external high-speed clock is ready or not

Warning
This field is read-only

◆ HSEBYP

t_u32 HSEBYP

External high-speed clock bypass.

Bypass the oscillator with an external clock

◆ CSSON

t_u32 CSSON

Clock security system enable.

Enable or disable the clock security system

◆ __pad1__

t_u32 __pad1__

Reserved bit(s)

Attention
This field is reserved and must be kept at reset value.

◆ PLLON

t_u32 PLLON

PLL enable.

Enable or disable the PLL

◆ PLLRDY

t_u32 PLLRDY

PLL clock ready flag.

This bit is set by hardware to indicate that the PLL clock is locked

Warning
This field is read-only

◆ __pad2__

t_u32 __pad2__

Reserved bit(s)

Attention
This field is reserved and must be kept at reset value.

The documentation for this struct was generated from the following file: